The present invention relates to methods of optical to electronic conversion, in particular to photo-detection with silicon-based devices suitable for integration with Complementary Metal Oxide Semiconductor (CMOS) technology.
Conventional Charge Coupled Devices (CCDs) and CMOS image sensors (CIS) comprise several elements that are key to high performance image sensing. The photo-diode, which converts light into electrical signals, the CMOS devices and circuits that handle the analog signal, convert it to a digital signal, and that perform digital signal processing, the color filters, etc. CIS technology has the advantage that all these elements can be monolithically integrated on the same “die” or “chip”, while CCDs can only monolithically integrate color filtering and photo-absorption.
In conventional CIS technology the built-in vertical pn-junctions, source-to-well and drain-to-well junctions, formed during the fabrication of the CMOS devices, are used as photo-diodes for light detection. The photo-detection capabilities depend on the intrinsic energy band-structure properties of silicon, such as the coefficient of absorption, and on several characteristics of the junctions, such as doping profiles, junction depth, depth of isolation structures (LOCOS or STI), etc.
The efficiency of light absorption by silicon is highly dependent on the wavelength. Photons of shorter wavelengths (photons with higher energy) are absorbed within shorter distances from the surface, than photons of longer wavelengths (photons with smaller energy). For silicon, in the visible range, photons of the color blue are absorbed very efficiently, but photons of the color red are not, and thus require a much longer “absorption depth”. Therefore, the absorption of photons of the color red places a limit on the minimum thickness of the light-absorbing region.
On the other hand, advancing CMOS technology consists in shrinking the lateral dimensions of transistors, which require also the shrinking of structures in the vertical direction, i.e., shallower, higher doped junctions. Essentially smaller MOSFETs require source and drain regions that are nearly or fully degenerately doped. Consequently, inside these semiconductor regions an electric field is very weak or completely shielded, thus leading to charge transport only through diffusion. Since for CIS devices light is absorbed in the source/drain region of a MOSFET, the absorption of very short wavelengths (shorter than Blue) takes place very near the surface, thus the electron-hole pairs have very short lifetimes, i.e., high recombination rates. Therefore the amount of charge collected is only a fraction of the total that is photo-generated. This explains the lower quantum efficiency of CIS devices for wavelengths that silicon absorbs very efficiently, such as UV radiation.
The requirements for efficient photo-absorption of the longer wavelengths, and for efficient collection of charge carriers photo-generated by shorter wavelengths, are in a collision course with the requirements for the continued scaling of CMOS technology, even on bulk substrates.
It is widely perceived that Thin-Film SOI substrates are highly beneficial, perhaps even a required to fabricate high performance sub-90 nm CMOS devices. The more advanced the CMOS technology, the greater the advantages of using Thin-Film SOI substrates. However, conventional CCDs and CIS devices utilize the bulk of the silicon wafer for photo-absorption, while with Thin-Film SOI the top silicon film, which is used to make CMOS devices, cannot efficiently absorb wavelengths in the visible, because it is too thin, i.e., the optical path inside the absorption film is too short.
Therefore, it can be said that conventional CIS technology is fundamentally incompatible with Thin-Film SOI substrates, and consequently incompatible with the requirements for high performance sub-90 nm CMOS technologies. It can then be concluded that conventional CMOS image sensors will not be able to take advantage of the well known benefits of CMOS scaling, also known as “Moore's Law”, in terms of speed, density, power dissipation and cost.
More advanced CMOS devices are important both inside the pixels and at the periphery of the sensor matrix. Active-pixel sensors require in-pixel transistors, which take area that does not contribute to photo-absorption. The ratio of the sensor-area over the total area of the pixel is called the “Fill Factor”. The inability to scale the size of CMOS devices will ultimately result in the impossibility to scale the size of pixels of CIS. Consequently this will also put a limitation on how small the entire image sensor can be for a given resolution, which in turn places constraints on the design of the optical system (lenses), thereby impacting the overall system size, weight, cost, etc.
The scaling of the pixel size of CMOS image sensors is also limited by the resolution of the lens system. The quality of the image captured by a CCD or CMOS image sensor matrix, degrades if the pixel size becomes smaller than the minimum feature possible to resolve by the lens system. It is therefore pointless to scale the pixel size below what the lens system can resolve. On the other hand the cost of a lens system increases for higher resolution lenses.
The principles of optical physics used for the design of conventional lens systems are “diffraction limited”. This means that it is not possible to design a lens system having a resolution approaching the wavelength of the light that it is meant to focus, even with the non-realistic assumption that the lenses could be manufactured with infinite precision.
Conventional CIS architectures consist of having the source/drain-to-well (vertical) pn-junction of a MOSFET to be also a photo-diode. Such architecture cannot be implemented in Thin-Film Silicon-On-Insulator (TF-SOI) substrates, also known as Fully-Depleted SOI (FD-SOI), in which such (vertical) pn-junction does not exist, since the source and drain regions of MOSFETs are formed directly on the buried oxide, rather than on a semiconductor region doped with impurities of opposite polarity. However, even if such junctions did exist on Thin-Film SOI CMOS devices, since the crystalline silicon film is so thin, typically less than 30 nm, the absorption of light in the visible range would be very inefficient, and insufficient to be of practical use for image sensors.
The present invention discloses a solution to enable the fabrication of high performance CMOS image sensors using Thin-Film SOI substrates. In addition to the advantages derived from more advanced CMOS devices, such as speed, power consumption, and reduced size, SOI substrates have a qualitative difference with respect to bulk substrates: it is easy to remove the back-side of the SOI substrate, and replace it with a different substrate which is transparent to light. Even though this is possible with both Thick-Film SOI and Thin-Film SOI, there are more advantages to using Thin-Film SOI substrates, as it will be described below.
In conventional CCDs and CIS, color filtering is implemented by fabricating a checkerboard pattern, known as the “Bayer Pattern”, in which filters for different colors, typically Red, Green and Blue, alternate across adjacent pixels. The complementary primary colors, Cyan, Yellow and Magenta can also be used. The color filters do not need to be restricted or limited to the usual three primary color pixels. Since conventional Color CMOS Image Sensors are made on bulk silicon wafers, only front-side illumination is possible.
The materials used to fabricate the color filters are not compatible with silicon processing, and conventional color CIS have the color filters made on top of a passivation layer, deposited over the last metallization level. As the number of metal levels increases, so does the distance between the surface of the silicon wafer, where light is absorbed, and the color filters. More metal levels lead to increased color crosstalk between adjacent pixels because more photons impinging at angles far from the normal to the substrate travel through color filters and are absorbed in photo-diodes that do not belong to the same pixels. This is a very important factor, which in practice has limited the number of metal layers 3 or 4, while the leading edge CMOS technologies can have 6 or 7 metal layers. The limitation on the number of metal levels places severe consequences on the “system architecture” that can be fabricated on the same die, thus monolithically integrated, with the image sensors. Advanced digital signal processing, needed for image compression for example, requires the availability of microprocessor and/or digital signal processor cores, which typically demand more metal levels than just 3 or 4.
“Front-side” illumination also requires the light sensing regions not to be blocked by metal lines, thereby placing severe restrictions on the metal lines connecting the in-pixel circuitry to the peripheral circuitry. This limitation to the metal interconnects between the pixels and the periphery limits the maximum bandwidth available for the pixel-to-periphery communications, which in turn has detrimental consequences for parameters such as maximum frame rate, dynamic range, etc.
Back-side illumination of photo-diodes made on Thin-Film SOI is an architectural feature with the potential for many cascading effects on the overall architecture of image sensors. It becomes possible to monolithically integrate different types of structures on the back of the buried oxide, which is impossible to do with bulk substrates, since they require front-side illumination.
Some of these structures do not require any particular layout or processing features on the front side. Examples are conventional color filters, and nano-optics structures, such as Surface-Plasmon Polariton (SPP) structures. Other structures, such as resonant cavities, may require particular layouts of layer thicknesses on the front-side. It must be emphasized that any of these structures per se, or combined in some fashion, are impossible to implement with bulk substrates. As it will be described later, processing the back-side of the wafer and back-side illumination can be taken advantage of for the implementation of completely new structures that will break through the limitations of conventional optical systems, including the fabrication of monolithically integrated lens system capable of sub-wavelength resolution, thereby motivating and justifying the development of sub-wavelength sized pixels, which in turn demand more advanced CMOS technologies.
Therefore, using TF-SOI or TF-GeOI substrate for CMOS image sensors, enabling back-side illumination, is the basic building block for radically new architectures and technologies that overcome the fundamental limitations of conventional imaging systems, composed of image sensors, wavelength filters, lens group.